Flash memory module, storage apparatus using flash memory module as storage medium, and address translation table verification method for flash memory module

ABSTRACT

An purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. 
     A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application relates to and claims priority from Japanese PatentApplication No. 2007-3050, filed on Jan. 11, 2007, the entire disclosureof which is incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The invention relates to a flash memory module, a storage apparatususing the flash memory module as a storage medium, and an addresstranslation table verification method for the flash memory module,particularly to those suitable for use in verification of an addresstranslation table used for accessing data stored in a flash memorymodule.

2. Description of Related Art

Generally, a storage apparatus has a randomly accessible nonvolatilestorage medium, such as a magnetic disk or an optical disk.

Meanwhile, collectively erasable nonvolatile semiconductor storagemedia, such as flash memory, have been being developed with thedevelopment of semiconductor techniques. In a flash memory module, aflash memory controller in the module refers to an address translationtable to translate a logical page address into a physical page address,and stores data to a flash memory chip. Storage apparatuses that use theflash memory module as a storage medium are considered as more favorablein terms of durability, power-save performance, and access time, etc.,than storage apparatuses having a number of small disk drives such asmagnetic disks.

A method for preventing inappropriate mapping in an address translationtable in a flash memory module exists (see Japanese Patent Laid-OpenPublication No. 2003-337757). That conventional technique is designed toprevent inappropriate mapping that may occur when valid logical pageaddress data is garbled into invalid data.

As described above, storage apparatuses using a flash memory module as astorage medium are considered as being able to save more power thanthose using magnetic disks or similar. However, comparing powerconsumption values in a currently commercial 2.5 inch hard disk driveand in a 2.5 inch hard disk drive compatible flash memory module in anexample, the power consumption value during data writing/reading (R/W)in the flash memory module is 2.9 watt, and that in the hard disk driveis 2.3 watt. The power consumption value in the flash memory module is alittle larger than that in the hard disk drive. During idling, the powerconsumption value in the flash memory module is 2.2 watt, and that inthe hard disk drive is 1.2 watt. The power consumption value in theflash memory module is about twice that in the hard disk drive.

A flash memory chip itself consumes a very little power, as the powerconsumption per chip during idling is on the sub-milliwatt level.Accordingly, a large part of the power consumption in the flash memorymodule during idling can be considered as being derived from the flashmemory controller. Therefore, it is essential to conserve the powerconsumption in the flash memory controller during idling to takeadvantage of the low power consumption characteristics of the flashmemory chip.

Commonly, a flash memory controller is a CMOS LSI (Complementary MetalOxide Semiconductor Large Scale Integration). In a CMOS LSI, powerconsumption can be saved by decreasing power supply voltage or loweringoperating frequency. Accordingly, it can be assumed that the powerconsumption in a flash memory will become lower by decreasing powersupply voltage, halting operation, or lowering operating frequency inthe flash memory controller.

Meanwhile, an address translation table in a flash memory controller isstored in RAM. For example, SRAM (Static Random Access Memory) is usedbecause high-speed access characteristics are required in RAM. In SRAM,soft errors occur due to radiation in some cases, at a very small rate.If the power consumption in a memory controller is lowered, thepossibility that a soft error in data written to an address translationtable occurs during low power operation mode increases.

To address the thus caused soft errors, data is guaranteed against softerrors generally by adding error correction information to data storedin an address translation table and verifying the address data and theerror correction information added to that address data when reading thedata. In other words, accessed data in SRAM is guaranteed by the errorcorrection information, but data that is not accessed is not guaranteedagainst errors. Accordingly, because an address translation table storedin SRAM is not accessed during low power consumption mode involving haltof operation in a flash memory controller, the data cannot be verifiedby detecting and correcting any soft error that occurs during low powerconsumption mode. Moreover, during low power consumption mode involvingreduced operating frequency too, a soft error cannot be detected unlessdata in an address translation table is accessed.

A soft error that has occurred during low power consumption mode can befirst detected when error data in an address translation table isaccessed after returning to regular mode. Therefore, if low powerconsumption mode continues for a long period of time, soft errors mayaccumulate in the address translation table and those errors may not beable to be corrected any more from the error correction information. Inthat case, it is necessary to access a flash memory chip connected tothe flash memory controller, read address information, and reconfigurethe address translation table in the SRAM. It takes about 1-2 secondsper flash memory chip to reconfigure the address translation table.Therefore, if a large number of chips are connected to a flash memorycontroller, it takes a long period of time to reconfigure the addresstranslation table. For storage apparatuses, from which high speed accessis required, a long time taken to reconfigure the address translationtable when returning from low power consumption mode to regular mode isnot acceptable.

Japanese Patent Laid-Open Publication No. 2003-337757 lacksconsideration for lowering power consumption. Moreover, the techniquedisclosed in that document cannot address common soft errors that mayoccur in an address translation table. In other words, that technique isdesigned to prevent inappropriate mapping that may be made when a validlogical page address is garbled into a invalid logical page address.However, if a valid logical page address is garbled, generally speaking,it is not always garbled into a invalid logical page address. Forexample, it is possible that a valid logical page address is garbledinto another valid logical page address. In that case, errors in theaddress translation table cannot be verified with the techniquedisclosed in Japanese Patent Laid-Open Publication No. 2003-337757.

The invention has been made in light of the above described points, andits object is to propose a flash memory module able to immediatelyreturn from low power consumption mode to regular mode by verifying datain an address translation table in the flash memory module during lowpower consumption mode, a storage apparatus using that flash memorymodule as a storage medium, and a method for verifying an addresstranslation table in the flash memory module.

SUMMARY

The invention provides a flash memory module including a flash memorycontroller and at least one flash memory chip, the flash memorycontroller having memory that stores an address translation table fortranslating between a logical page address and a physical page addressin the flash memory chip, and the flash memory controller controlling afirst operation of reading/writing data and a second operation ofoperating in an idling state at lower power consumption than during thefirst operation by halting operation, decreasing power supply voltage,or lowering operating frequency, wherein data in the address translationtable is verified during the second operation.

In that flash memory module, data errors in the address translationtable can be detected and corrected by verifying data in the addresstranslation table during low power consumption mode involving any ofhalting operation, decreased power supply voltage, or lowered operatingfrequency, and the flash memory module can immediately return from lowpower consumption mode to regular mode, preventing occurrence of errorsthat cannot be corrected with error correction information.

With this invention, a flash memory module that can immediately returnfrom low power consumption mode to regular mode by verifying data in anaddress translation table in a flash memory module during low powerconsumption mode, a storage apparatus using that flash memory module asa storage medium, and a method for verifying the address translationtable in the flash memory module can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the storage apparatus configuration inthe invention.

FIG. 2 is a block diagram showing the channel adapter configuration inthe invention.

FIG. 3 is a block diagram showing the storage adapter configuration inthe invention.

FIG. 4 is a block diagram showing the flash memory module configurationin the invention.

FIG. 5 is a diagram illustrating a block in the flash memory module inthe invention.

FIG. 6 is a diagram illustrating components relating to powerconsumption control in the flash memory controller in the invention.

FIG. 7 is an address translation table in the invention.

FIG. 8 is a diagram showing an example of data stored in the register inthe invention.

FIG. 9 is a diagram showing an example of data stored in the register inthe invention.

FIG. 10 is a diagram illustrating power supply voltage and body bias inthe invention.

FIG. 11 is a diagram showing the flash memory module management table inthe invention.

FIG. 12 is a diagram showing the RAID group management table in theinvention.

FIG. 13 is a flowchart illustrating low power consumption mode in theflash memory module in the invention.

FIG. 14 is a flowchart illustrating data verification in the addresstranslation table performed during low power consumption mode in theinvention.

FIG. 15 is a diagram illustrating execution of data verification for theaddress translation table at low duty cycle according to the invention.

FIG. 16 is a flowchart illustrating the table reconfiguration processingin the invention.

FIG. 17 is a flowchart illustrating the method for having all flashmemory modules in a RAID group shift to low power consumption mode inthe invention.

FIG. 18 is a flowchart illustrating the method for having all flashmemory modules in a RAID group shift to regular mode in the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

An example of a flash memory module, a storage apparatus, and an addresstranslation table verification method for the flash memory module in theinvention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a storageapparatus 100. The storage apparatus 100 includes a storage controllerSC and flash memory modules P00-P33.

The storage controller SC includes channel adapters CA0 and CA1, cachememories CM0 and CM1, storage adapters SA0 and SA1, and interconnectionnetworks NW0 and NW1. Although there are only two channel adapters (CA0and CA1), cache memories (CM0 and CM1), and storage adapters (SA0 andSA1), any number may be provided.

The interconnection networks NW0 and NW1, such as switches, mutuallyconnect devices included in the storage controller SC. Morespecifically, the interconnection networks NW0 and NW1 mutually connectthe channel adapter CA0, cache memory CM0, and the storage adapter SA0,and also mutually connect the channel adapter CA1, cache memory CM1, andstorage adapter SA1.

The channel adapter CA0, which will be described later referring to FIG.2, is connected, via channels C00, C01, C02, and C03, to an externalhost computer (not shown in the figure). Similarly the channel adapterCA1 is connected, via channels C10, C11, C12, and C13, to the externalhost computer (not shown). Examples of the host computer include acomputer that reads/writes data from/to the storage apparatus 100 inthis embodiment.

The cache memories CM0 and CM1 temporarily store data received from thechannel adapters CA0 and CA1 and the storage adapters SA0 and SA1.

The storage adapter SA0, which will be described later referring to FIG.3, is connected to the flash memory module P00 or another one. Morespecifically, the storage adapter SA0 is connected, via channels D00,D01, D02, and D03, to the flash memory modules P00-P03, P10-13, P20-23,and P30-33, respectively.

Similarly, the storage adapter SA1 is also connected to the flash memorymodule P00 or another one. More specifically, the storage adapter SA1 isconnected, via channels D10, 11, 12, and D13, to the flash memorymodules P00-P03, P10-P13, P20-23, and P30-P33.

The channel adapters CA0 and CA1 and the storage adapters SA0 and SA1are connected to a maintenance terminal SVP. The maintenance terminalSVP sends setting information input by an administrator of the storageapparatus 100 to the channel adapters CA0 and CA1 and/or the storageadapters SA0 and SA1.

The storage apparatus 100 may include a single adapter instead of thestorage adapter SA0 and the channel adapter CA0. In that case, thesingle adapter performs processing for the storage adapter SA0 and thechannel adapter CA0.

VDEV0-VDEV3 are RAID (Redundant Arrays of Inexpensive Disks) groups. Forexample, the RAID group VDEV0 consists of the flash memory modules P00,P10, P20, and P30. If an error occurs in one of the flash memory modulesincluded in the RAID group, e.g. the flash memory module P00, and datacannot be read, the data can be rebuilt from the other flash memorymodules P10, P20, and P30 included in the same RAID group.

The flash memory modules P00-P33 are connected, via the networks N00 andN01, to the storage adapters SA0 and SA1, respectively. The storagecontroller SC controls electric power consumed in the flash memorymodules P00-P33 via the networks N00 and N01. The storage adapters SA0and SA1 can monitor condition settings for low power consumption modeand low power consumption mode status in the flash memory modulesP00-P33.

FIG. 2 is a block diagram showing the configuration of the channeladapter CA0. The channel adapter CA0 includes a host channel interface21, cache memory interface 22, network interface 23, processor 24, localmemory 25, and processor-peripheral controller 26.

The host channel interface 21 is an interface connected to an externalhost computer (not shown) via the channels C00, C01, C02, and C03. Thehost channel interface 21 mutually converts between the data transferprotocol in the channels C00, C01, C02, and C03 and that in the storagecontroller SC.

The cache memory interface 22 is an interface connected to theinterconnection networks NW0 and NW1. The network interface 23 is aninterface connected to the maintenance terminal SVP. The host channelinterface 21 and the cache memory interface 22 are mutually connectedvia a signal line 27.

A processor 24 performs various types of processing by executingprograms stored in local memory 25. More specifically, the processor 24controls data transfer between the host computer (not shown) and theinterconnection networks NW0 and NW1.

The local memory 25 stores the programs executed by the processor 24 andtables referred to by the processor 24. Those tables are set or modifiedby the administrator.

When doing so, the administrator inputs information concerning settingsor modification in the tables to the maintenance terminal SVP. Themaintenance terminal SVP sends the input information to the processor 24via the network interface 23. The processor 24 produces or modifies thetables based on the received information, and stores the tables in thelocal memory 25.

The processor-peripheral controller 26 controls data transfer betweenthe host channel interface 21, cache memory interface 22, networkinterface 23, processor 24, and local memory 25. Examples of theprocessor-peripheral controller 26 include a chipset. As theconfiguration of the channel adapter CA1 is same as that of the channeladapter CA0, its explanation will be omitted.

FIG. 3 is a block diagram showing the storage adapter SA0 configuration.The storage adapter SA0 includes a cache memory interface 31, storagechannel interface 32, network interface 33, processor 34, local memory35, and processor-peripheral controller 36.

The cache memory interface 31 is an interface connected to theinterconnection networks NW0 and NW1.

The storage channel interface 32 is an interface connected to thechannels D00, D01, D02, and D03, and mutually converts between the datatransfer protocol in the channels D00, D01, D02, and D03 and that in thestorage controller SC. The cache memory interface 31 and the storagechannel interface 32 are mutually connected via a signal line 37.

The network interface 33 is an interface connecting the storage adapterSA0, management terminal SVP, and flash memory modules P00-P33.

The processor 34 performs various types of processing by executingprograms stored in the local memory 35.

The local memory 35 stores the programs executed by the processor 34 andtables referred to by the processor 34. The tables are set or modifiedby the administrator.

When the tables are set or modified, the administrator inputsinformation concerning setting or modification in the tables to themanagement terminal SVP. The management terminal SVP sends the inputinformation to the processor 34 via the network interface 33. Theprocessor 34 prepares or modifies the tables based on the receivedinformation, and stores the tables in the local memory 35.

The processor-peripheral controller 36 controls data transfer betweenthe cache memory interface 31, storage channel interface 32, networkinterface 33, processor 34, and local memory 35. Examples of theprocessor-peripheral controller 36 include a chipset. As the storageadapter SA1 has the same configuration as that of the storage adapterSA0, its explanation will be omitted.

FIG. 4 is a block diagram showing the configuration of the flash memorymodule P00. The flash memory module P00 includes a flash memorycontroller MC, flash memory MEM, and power supply (PS) 408. The flashmemory MEM stores data. The flash memory controller MC reads, writes, orerases data to/from the flash memory MEM. The power supply 408 convertselectric power externally supplied into voltage for use in the flashmemory module P00, and supplies the power to the flash memory controllerMC and flash memory MEM.

The flash memory controller MC includes a processor (μP) 401, interfaceunit (DKC I/F) 402, internal bus (BUS) 403, memory (RAM) 404, memory(ROM) 407, power controller (PCTL) 409, flash memory interface unit (FMI/M) 410, and data transfer unit (DMA) 411.

The flash memory MEM includes a flash memory chip 405. The flash memorychip 405 includes blocks 406 and stores data. As will be described laterwith reference to FIG. 5, a block also constitutes the unit for dataerasure performed by the flash memory controller MC.

The interface unit 402 is respectively connected, via the channels D00and D10, to the storage adapters SA0 and SA1 in the storage controllerSC.

The interface unit 402 receives a command from the storage adapters SA0and SA1. Examples of the command from the storage adapters SA0 and SA1include a serial-ATA command and an SCSI command. More specifically, theinterface unit 402 receives data from the storage adapters SA0 and SA1and stores the received data in the memory 404. The interface unit 402also sends data stored in the memory 404 to the storage adapters SA0 andSA1.

The memory 404, such as SRAM, can read/write data at a high speed, andtemporarily stores data transmitted/received by the interface unit 402.The memory 407 is a nonvolatile memory and stores programs executed bythe processor 401. Those programs are copied from the memory 407 to thememory 404 at start-up of the storage apparatus 100 so that theprocessor 401 can execute the programs. The memory 404 also storestables referred to by the processor 401.

Examples of the tables include a table for translating between a logicalpage address and physical page address for the flash memory MEM. Thelogical page address is an address used for accessing a page, which is aunit of data read/write in the flash memory MEM, from the external ofthe flash memory module P00 (e.g., from the storage adapter SA0). Thephysical page address is an address used by the flash memory controllerMC to access a page, which is a unit of data read/write in the flashmemory MEM.

An internal bus 403 mutually connects the processor 401, interface unit402, memory 404, memory 407, data transfer unit 411, and flash memoryinterface unit 410, and functions as a data transfer path.

The power controller 409 controls power consumption in the flash memorycontroller MC, and is connected, via the networks N00 and N01, to thestorage adapters SA0 and SA1 respectively.

The flash memory interface unit 410 is an interface connecting the flashmemory controller MC and the flash memory chip MEM.

The data transfer unit 411 controls read/write data transfer between theflash memory chip MEM and memory 404 under the command of the processor401. If the function of the data transfer unit 411 is executed by theprocessor 401, the data transfer unit 411 may be omitted.

The processor 401 performs various types of processing by executing theprograms stored in the memory 404. For example, the processor 401 refersto the address translation table (which will be described laterreferring to FIG. 7) for translating between the logical page addressand physical page address in the flash memory MEM stored in the memory404, and reads/writes data from/to the flash memory MEM.

FIG. 7 is a diagram showing the address translation table stored in thememory 404. The address translation table T1 contains logical pageaddresses 701, physical page addresses 702 corresponding the logicalpage addresses 701, and error correction information 703. Examples ofthe error correction information 703 include Hamming code. Errors can bedetected and corrected by using the logical page address 701, physicalpage address 702, and error correction information 703 stored in theaddress translation table T1.

The processor 401 performs reclamation processing (block reclamationprocessing) and wear leveling processing (number-of-erasure levelingprocessing), which will be described later, on the blocks 406 in theflash memory module P00.

As the other flash memory modules P01-P33 have the same configuration asthat of the flash memory module P00, their explanation will be omitted.

FIG. 5 is a diagram illustrating the block 406 in the flash memorymodule P00. The block 406 includes pages 501. Generally, the block 406includes several dozens of pages 501 (e.g., 64 pages).

The page 501 is a unit of data read/written by the flash memorycontroller MC. For example, in an NAND-type flash memory, the flashmemory controller MC reads data at a speed of 20-30 or less μs/page,writes data at a speed of 0.2-0.3 ms/page, and erases data at a speed of2-4 ms/block.

Each page 501 includes a data section 502 and redundancy section 503.For example, the page 501 has 2112-byte capacity per page, and includesthe data section 502 of 2048 bytes and the redundancy section 503 of 64bytes. The data section 502 stores normal data. The redundancy section503 stores management information and error correction information forthe page 501.

The management information contains an offset address and page status.The offset address is a relative address in the block 406 the page 501belongs to. The page status indicates that the page 501 is “valid,”“invalid,” “unused,” or “under processing.”

The error correction information is information used for detecting andcorrecting errors in the page 501, and examples include Hamming code.

Usually, only the flash memory controller MC can access the redundancysection 503 in the page, and the storage adapters SA0 and SA1 can accessonly the data section 502 in the page. In other words, the logical pageaddress maps the memory space in the data section 502 in the page.

In the flash memory module P00, by its very nature, data “1” can bewritten over “0” in the block 406 but “0” cannot be written over “1.” Inother words, the data cannot be modified directly. The flash memorycontroller MC writes data in an unused page in a block. The processingreferred to as “reclamation processing” (block reclamation processing)is processing for saving, to another block, valid data in a firstblock—in which unused pages are no longer left and so no more data canbe written—, and then erasing the data in the first block so that datacan be written.

In this way, updating of data in the flash memory module P00 isaccompanied by erasure of data in the block 406. However, the time takento erase one block 406 is longer than the time taken to write data forone page 501 by one power of 10. Accordingly, if one block 406 is erasedevery time data in the page 501 is updated, the data updatingperformance in the flash memory module P00 considerably deteriorates. Inother words, it is necessary in the flash memory module P00 to use analgorithm with which the erasing time can be reduced.

Also, there is a limitation on the number of erasures possible for theblocks 406 in the flash memory module P00. For example, only up to100,000 erasures are guaranteed per block 406. Accordingly, in a block406 where data updating has been concentrated, resulting in the numberof times of data erasures being incremented, data becomes inerasable,and that block becomes unavailable. Therefore, wear leveling processingis performed in the storage apparatus 100 using the flash memory moduleP00 as a storage medium so that erasures do not concentrate in aspecific block 406.

For the above described erasure time reduction and wear leveling,address translation processing for translating a logical page addressinto a physical page address is performed in the flash memory module P00when data is written. More specifically, the flash memory controller MCtranslates a logical page address received from a host device (notshown) as a data write target address into a physical page address,which is a real data write address in the flash memory chip, byreferring to the address translation table T1 to avoid concentration ofdata write to a specific physical page address. Therefore, a dataguarantee for the address translation table T1 is always required in theflash memory module P00.

For the above described reclamation processing or wear levelingprocessing, in some cases the data written to the flash memory moduleP00 is moved in the flash memory module P00 without a command from thestorage controller SC. If the result of the data movement is correctlyreflected in the address translation table storing the logical andphysical page addresses, the storage controller SC becomes able toaccess the appropriate data.

However, if a soft error occurs in data in the address translation tableT1 because of data garbling in the table caused by radiation or similar,the error occurs in a data read/write target address in the flash memorymodule P00, so the storage controller SC cannot read the appropriatedata.

Next, power consumption control in the flash memory controller MC willbe described. FIG. 6 is a diagram illustrating the components relatingto the power consumption control in the flash memory controller MC. Thepower controller 409 has a register 606 for setting operating conditionsduring low power consumption mode. The data to be stored in the register606 will be described later (FIGS. 8 and 9). The data stored in theregister 606 can be set and monitored, via the networks N00 and N01,from the storage adapters SA0 and SA1.

The power supply 408 reads, via the signal line 604, the set conditionsstored in the register 606, and supplies electric power, via the chippower supply lines 601, to the processor 401, interface unit 402, memory404, memory 407, flash memory interface unit 410, and data transfer unit411 according to the set conditions. The power supply 408 also thesupply power for body biasing via the chip power supply line 603. A bodybias controller 608 reads the set conditions stored in the register 606via the signal line 607 and distributes body biasing power, via a chippower supply line 605, to the processor 401, interface unit 402, memory404, memory 407, flash memory interface unit 410, and data transfer unit411 in the flash memory controller MC.

A clock controller 615 reads the set conditions stored in the register606 via a signal line 611, converts, according to the set conditions, areference clock signal input from the signal line 616, and distributesthe converted clock signal to the processor 401, interface unit 402,power controller 409, flash memory interface unit 410, and data transferunit 411 via signal lines 612, 613, and 614.

The processor 401 sends a signal for determining whether or not topermit the power controller 409 to interrupt via the signal line 610.The power controller 409 sends an operation halt signal or operationresumption signal to the processor 401 via the signal line 609.

If the interface unit 402 receives a low power consumption command, suchas Serial-ATA Slumber command or SCSI Start/Stop Unit command, theinterface unit 402 notifies, via the signal line 602, the powercontroller 409 of reception of the low power consumption command.

FIGS. 8 and 9 are diagrams illustrating the data stored in the register606 in the power controller (PCTL) 409. The register 606 in the powercontroller 409 includes register A (FIG. 8) and register B (FIG. 9).

FIG. 8 is a diagram illustrating the data stored in the register A. Theregister A mainly stores parameters for controlling conditions for shiftof the flash memory modules P00-P33 to low power consumption mode. Aparameter 801 sets whether the flash memory modules P00-P33automatically shift to low power consumption mode, or shift to low powerconsumption mode according to a command received from the storageadapter SA0 or SA1, etc., or both.

The parameter 802 sets whether or not data verification is to beperformed on the address translation table T1 during low powerconsumption mode. If the data verification is not performed on theaddress translation table T1, the power consumption becomes lower thanwhen the data verification is performed but address information has tobe re-read from the flash memory chip 405 when returning to regularmode.

The parameter 803 stores shift conditions applied if the automatic modeis set for shifting to low power consumption mode in the parameter 801.For example, if no access is made to the flash memory modules P00-P33within the time stored in the parameter 803 and the parameter 801 is setto the automatic mode, the flash memory modules P00-P33 automaticallyshift to low power consumption mode.

The parameter 804 indicates whether the current operation is regularmode or low power consumption mode. The storage adapters SA0 and SA1 canfind the operation status of the flash memory modules P00-P33 bychecking the parameter 804. The parameter 805 indicates the number oferrors that has occurred in the address translation table T1, thatcannot be corrected only with the error correction information.

FIG. 9 is a diagram illustrating data stored in the register B. Theregister B stores parameters for controlling operating conditions forthe flash memory modules P00-P33 during low power consumption mode.Items 901-906 in the register B indicate power control targets in theflash memory controller MC. Items 907-909 show operating conditionschanged for lowering power consumption. The items 907 and 908 indicatethe conditions of power supply voltage and body bias voltage supplied tothe processor 401, interface unit 402, memory 404, memory 407, and flashmemory interface unit 410, and data transfer unit 411 during low powerconsumption mode. The power supply voltage and body bias voltage will bedescribed later. The item 909 indicates the operating frequencies of theprocessor 401, interface unit 402, memory 404, memory 407, flash memoryinterface unit 410, and data transfer unit 411 during low powerconsumption mode. The lower the operating frequency is, the greater thepower consumption lowering effect is. To halt the operation, thefrequency is set to “0.” The items 902 and 903 are control parametersfor the memory (RAM 404 and ROM 407). Since the operating frequency ofthe memory (RAM 404 and ROM 407) is determined based on the accesssignal frequency, the operating frequency during low power consumptionmode does not have to be set.

FIG. 10 is a diagram illustrating the power supply voltage and body biasvoltage. To the inverter circuit INV, positive chip power supply VDD1 orVDD2, negative chip power supply VSS1 or VSS2, positive body bias VSUB1or VSUB2, and negative body bias VSUB3 or VSUB4 are supplied. It isassumed that VDD1, VSS1, VSUB1, and VSUB3 represent the power supplyvoltage supplied to the circuit during regular mode, and VDD2, VSS2,VSUB2, and VSUB4 represent the power supply voltage supplied to thecircuit during low power consumption mode.

For example, during regular mode, power is supplied to the circuit withprescribed voltage where VDD=VSUB1 and VSS1=VSUB3. Meanwhile, during lowpower consumption mode, power is supplied with voltage under theconditions where VDD1>VDD2 and VDD2<VSUB2, and VSS2≧VSS1 and VSS2>VSUB4.The operating power of the circuit is lowered by lowering the powersupply voltage, and appropriate body bias application lowers the powerconsumption due to leak current reduction.

FIG. 11 is a diagram illustrating the flash memory module managementtable T2 managed in the storage adapter SA0 or SA1. The storage adaptersSA0 and SA1 can monitor or modify the settings of the content of theregisters A and B by accessing the flash memory modules P00-P33 via thenetwork N00 or N01. The flash memory module management table T2 shown inFIG. 11 stores, to manage the parameters stored in the registers A and Bin each flash memory module P00-P33, a flash memory module identifier1001, the register A content 1002, and the register B content 1003 ineach flash memory module P00-P33. FIG. 12 is a diagram illustrating aRAID group management table T3 managed in the storage adapter SA0 orSA1.

The RAID group management table T3 shown in FIG. 12 stores a RAID groupidentifier 1201 and a group 1202 of the flash memory module identifiersthat form each RAID group. The RAID group management table T3 is used inthe flowcharts in FIGS. 17 and 18 that will be described later.

FIG. 13 is a flowchart illustrating low power consumption mode in theflash memory module P00. As the same operation as in the flash memorymodule P00 is performed in the other flash memory modules P01-P33, itsexplanation will be omitted. The flowchart in FIG. 13 shows theprocessing performed when reception of a command sent externallytriggers shifting to low power consumption mode in the flash memorymodule P00.

In step ST101, the interface unit 402 receives a low power consumptioncommand from, for example, the storage adapter SA0 or SA1. Examples ofthat command include S-ATA Slumber command or SCSI Start/Stop Unitcommand. The interface unit 402 notifies the power controller 409 ofreception of the low power consumption command.

In step ST102, the power controller 409 checks whether or not theprocessor 401 permits interruption.

In step ST103, if interruption is not permitted (ST103: NO), theprocessing returns to step ST102 and the power controller 409 waits forinterruption permission. Examples of the factors for interruption beingnot permitted include that the processor 401 is executing the wearleveling processing for the flash memory chip 405. The reason is that insome cases the processor 401 executes the wear leveling processingduring the time period where there is no access for data read/write. Inthis embodiment, the flash memory module P00 does not shift to the powerconsumption operation during execution of the wear leveling processingbut waits for the completion of that processing. In other words, as willbe described later, the flash memory module P00 shifts from regular modeto low power consumption mode and data verification in the addresstranslation table T1 is performed after the wear leveling processingends.

In step ST103, if the processor 401 permits interruption (ST103: YES),the processings proceeds to step ST 104. In step ST104, the powercontroller 409 gives an operation halt order to the processor 401 viathe signal line 609.

In step ST105, the power controller 409 modifies the power supplyvoltage, body bias voltage, and clock frequency according to the setconditions in the register 606.

In step ST 106, the processor 401 executes the data verification in theaddress translation table T1. The detail of step ST106 will be describedlater referring to the flowchart in FIG. 14.

In step ST107, whether or not the interface unit 402 has received acommand (active command) to return from low power consumption mode toregular mode is checked. If the active command has been received (ST107:YES), the processing proceeds to step ST109.

In step ST109, the power controller 409 restores the power supplyvoltage, body bias voltage, and clock frequency to return to regularmode. In step ST110, the power controller 409 commands the processor 401to restart operation.

If the active command has not been received in step ST107 (ST107: NO),the power controller 409 waits for a prescribed period of time in stepST108. Within the prescribed period of time, the power controller 409repeats step ST107 and executes data verification in the addresstranslation table T1 in step ST106 in a fixed cycle. If the powerconsumption in the power controller 409 is sufficiently smaller thanthat in the processor 401, the power consumption in the flash memorycontroller MC can be lowered by reducing the ratio of the time periodfor the data check in the address translation table T1 performed by theprocessor 401.

FIG. 15 is a time chart illustrating execution of data verification inthe address translation table T1 at low duty cycle. The processor 401executes the data verification in the address translation table T1 oneportion (1/n) at a time so that the halt period is longer than the dataverification period, i.e., at low duty cycle.

As shown in FIG. 15, the cycle of execution of the data verification inthe address translation table T1 performed by the processor 401 on aprescribed range at a time is represented by “T.” Within cycle T, thetime period in which the processor 401 verifies data in the prescribedrange of the address translation table T1 is represented by “t.” Cycle Tand time period t, or cycle T and the prescribed range are set under thefollowing three conditions.

First, the first condition, i.e. the setting condition of cycle T willbe described. The time taken for the flash memory modules P00-P33 inthis embodiment to return from low power consumption mode to regularmode is the sum of cycle T and the time period taken, when the processor401 is operating, for the flash memory modules P00-P33 to shift toregular mode after receiving the active command. Cycle T is set so thatthe above sum is equal to or less than the waiting time acceptable forthe specifications of the storage apparatus 100.

Next, the second condition, i.e. the set condition a of time period t orthe data verification range performed within time period t will bedescribed. Cycle T and time period t, or cycle T and the range of dataverification executed by the processor 401 within time period t aredetermined so that the average power consumption during low powerconsumption mode accompanied by the data verification is an acceptablepower consumption for the storage apparatus 100 or less, in light of thetime taken by and the power consumed by the processor 401 for the dataverification in the prescribed range.

Next, the third condition, i.e. the set condition b of time period t orthe range of data verification executed within time period t will bedescribed. Cycle T and time period t, or the range of data verificationexecuted by the processor 401 within cycle T and time period t aredetermined so that all data in the address translation table T1 isverified at least once within the time period in which a one-bit softerror is statistically expected to occur in the address translationtables T1 in all flash memory modules P00-P33 mounted in the storageapparatus 100.

FIG. 14 is a flowchart illustrating data verification (step ST106) inthe address translation table T1 performed in the flash memory moduleP00 during low power consumption mode in this embodiment.

In step ST201, the power controller 409 shifts the operating conditionof the processor 401 and the memory 404 to regular mode and commands theprocessor 401 to restart operation. If data verification in the addresstranslation table T1 can be performed while the processor 401 and memory404 maintain low power consumption mode, the operating condition doesnot have to be shifted. In step ST202, the processor 401 sets, in theregister, a pointer to the data subjected to the data verification inthe address translation table T1.

In step ST203, the logical page address, physical page address, anderror correction information stored in the table is checked, and whetheror not there are any errors is determined in step ST204. If no error isfound in step ST204 (ST204: NO), the processing proceeds to step ST208.If a prescribed amount of data has been checked in step ST208 (ST208:YES), the processing proceeds to step ST209.

In the flash memory module P00 in this embodiment, all data in theaddress translation table T1 is not sequentially verified at a time, butexecution of the data verification is divided into several time periodsto reduce the average power consumption. In step ST209, the powercontroller 409 commands the processor 401 to halt operation. If theprocessor 401 and memory 404 have been shifted to regular mode in stepST201, the processor 401 and memory 404 are shifted again to low powerconsumption mode.

In step ST208, if verification on the prescribed amount of data has notyet finished (ST208: NO), a pointer for indicating the next data in theaddress translation table T1 is set in the register in step ST210, andthe processing returns to step ST203.

If any error is detected in step ST 204 (ST204: YES), whether or not theerror can be corrected is determined in step ST205. If the error can becorrected with the error correction information that has been added tothe data (ST205: YES), the processing proceeds to step ST207 andexecutes error correction.

Meanwhile, if the error cannot be corrected from the error correctioninformation, e.g. if the number of bits where the error has occurred islarge (ST205: NO), table reconfiguration processing in step ST206 isexecuted and the processing returns to step ST202.

Next, the table reconfiguration (step ST206) will be described. FIG. 16is a flowchart illustrating the table reconfiguration processing.

In step ST301, the power controller 409 increments the number ofuncorrectable error occurrences in the parameter 805 in the register A,and checks whether or not the value in the parameter 802 is a prescribedvalue or less in step ST302. If the number of error occurrences exceedsthe prescribed value (ST302: NO), the processing proceeds to step ST303.

In step ST303, the flash memory module (defective module) in which thenumber of error occurrences exceeds the prescribed number is replacedand data is rebuilt in a spare flash memory module (not shown). Forexample, if RAID level is 5th, this rebuilding is processing forperforming an exclusive OR calculation by having the storage adapter SA0or SA1 read data in the flash memory module that belongs to the sameRAID group as the defective module to reproduce the data that has beenstored in the defective module.

The rebuilding can be done quickly by connecting the spare flash memorymodule to the storage adapter SA0 or SA1 in advance. The spare flashmemory module prepares, when connected to the storage adapter SA0 orSA1, the address translation table T1 in its flash memory controller andis set to a standby state in low power consumption mode, which isaccompanied by execution of the data verification (ST106, FIG. 13) inthe address translation table T1 in FIG. 13. By setting the spare flashmemory module to the standby state, it can be used immediately whennecessary.

If the number of error occurrences is the prescribed number or less(ST302: YES), the processing proceeds to step ST304. In step ST304, theprocessor 401 sets a pointer to the start physical page address in theflash memory module P00.

In step ST305, the processor 401 reads logical page address informationbased on the physical page address and stores the address information inthe address translation table T1.

In step ST307, whether or not the pointer set in the processor 401 hasreached the end physical page address is checked. If the pointer is notindicating the end physical page address in step ST307 (ST307: NO), thepointer is moved so that the processor 401 can access the next physicalpage address in step 306.

In step ST307, the processing ends if the address check has beencompleted up to and including the end physical page address (ST307:YES).

As cases where the number of error occurrences stored in the parameter805 in the register A exceeds the prescribed number, two cases areconceivable: i.e., the case where the accumulated number of errorsincluding the past data verification results exceeds the prescribednumber, and the case where several errors occur during one check andexceed the prescribed number.

Next, the method with which the storage apparatus 100 in this embodimenthas all flash memory modules in RAID groups (VDED0-VDEV3) shift to lowpower consumption mode will be described. FIG. 17 is a flowchartillustrating the method.

The storage adapter SA0 or SA1 reads/writes data from/to the flashmemory modules in the RAID group (for example, VDED0: flash memorymodules P00, P10, P20, P30) almost synchronously. Accordingly, the pointin time when the flash memory modules in the RAID group shift to lowpower consumption mode is also synchronous. As an example, the casewhere the automatic mode is set for low power consumption mode in theflash memory module P00 will be considered below.

In step ST401, the storage adapter SA0 or SA1 detects the shift of anyflash memory module, e.g., the flash memory module P00, to low powerconsumption mode. That detection is enabled by having the storageadapter SA0 or SA1 monitor the register A in each flash memory moduleP00-P33.

In step ST402, the storage adapter SA0 or SA1 accesses the RAID groupmanagement table T3 illustrated in FIG. 12, and inspects the flashmemory modules P10, P20, and P30 that belong to the same RAID group(VDEV0) as the flash memory module P00 that has shifted to low powerconsumption mode.

In step ST403, whether or not there is any flash memory module that hasnot shifted to low power consumption mode in that RAID group (VDEV0) ischecked.

If any of those flash memory modules has not shifted to low powerconsumption mode in step ST403 (ST403: YES), the processing proceeds tostep ST404 and the storage adapter SA0 or SA1 issues a low powerconsumption command to the flash memory module in the RAID group thathas not shifted to low power consumption mode. Then the processingreturns to step ST403.

In step ST403, if there is no flash memory module that has not shiftedto low power consumption mode, i.e., if all flash memory modules P10,P20, and P30 in the RAID group (VDEV0) have shifted to low powerconsumption mode (ST403: NO), the processing ends.

Also, all flash memory modules return from low power consumption mode toregular mode synchronously in each RAID group (VDEV0-VDEV3).Accordingly, all flash memory modules in each RAID group can return toregular mode according to substantially the same flowchart as shown inFIG. 17.

Next, the method for returning from low power consumption mode toregular mode in units of RAID groups will be described below. FIG. 18 isa flowchart illustrating that method.

In step ST501, the storage adapter SA0 or SA1 commands any of the flashmemory modules in a RAID group (e.g., VDEV0: flash memory module P00) toshift from low power consumption mode to regular mode. In other words,the storage adapter SA0 or SA1 issues an active command to the flashmemory module P00.

In step ST502, the storage adapters SA0 or SA1 accesses the RAID groupmanagement table T3 illustrated in FIG. 12 and inspects the flash memorymodules that belong to the same RAID group as the flash memory modulethat was ordered to shift to regular mode. For example, if the flashmemory module P00 was ordered to shift to regular mode, the flash memorymodules P10, P20, and P30 are inspected.

In step ST503, whether or not there is any flash memory module that hasnot shifted from low power consumption mode to regular mode is checked.

If any flash memory module in the RAID group has not shifted from lowpower consumption mode to regular mode (ST503: YES), the storage adapterSA0 or SA1 issues an active command to the flash memory module that hasnot shifted from low power consumption mode to regular mode in that RAIDgroup, and the processing returns to step ST503.

In step ST503, if there is no flash memory module that has not shiftedfrom low power consumption mode to regular mode in the RAID group, i.e.if all flash memory modules P10, P20, and P30 in the RAID group haveshifted to regular mode (ST503: NO), the processing ends.

In this way, the storage adapter SA0 or SA1 can manage the electricpower in the flash memory modules in units of RAID groups bysynchronizing those flash memory modules to lower the power consumption.Accordingly, a great power consumption lowering effect can be acquired,and the load deriving from the power consumption control on the storageadapter SA0 or SA1 is reduced.

As described above, each flash memory module P00-P33 in this embodimentincludes the flash memory controller MC and flash memory chip 405. Theflash memory controller MC has the memory (SRAM) 404 that stores theaddress translation table T1 used for translating between the logicalpage address and the physical page address in the flash memory chip 405,and controls the first operation, i.e. regular mode of data read/writeand the second operation, i.e. low power consumption mode in which theflash memory module operates in a standby state at lower powerconsumption than during regular mode of data read/write by decreasingthe power supply voltage or lowering operating frequency.

The flash memory modules P00-P33 can detect and correct soft errorsoccurring in data in the address translation table T1 during low powerconsumption mode by verifying the data in the address translation tableT1 during low power consumption mode. In other words, the powerconsumption in the flash memory modules P00-P33 can be saved, and thedata in the address translation table T1 in the flash memory controllerMC can be protected during low power consumption mode. Therefore, theaddress translation table T1 that becomes necessary if errors haveaccumulated does not have to be reconfigured when the flash memorymodules return from low power consumption mode to regular mode, and theflash memory modules P00-P33 in low power consumption mode canimmediately return to regular mode.

Moreover, the flash memory controller MC alternately executes the dataverification for the time period t for verifying data in the addresstranslation table T1 and the operation halt for the time period in whichthe operation of the flash memory controller MC is stopped, and the dataverification time period t is shorter than the operation halt timeperiod. Accordingly, the data verification is performed at low dutycycle.

If a spare flash memory module can be connected in advance to thestorage adapter SA0 or SA1, data can be rebuilt when errors that cannotbe corrected with the error correction information occur in any of theflash memory modules P00-P33 (defective module), by rebuilding the datafrom another flash memory module in the same RAID group to the spareflash memory module. Accordingly, the storage apparatus can immediatelyreturn to regular mode.

In the above described embodiment, the invention is used in the flashmemory modules P00-P33 configured as illustrated in FIGS. 5 and 6 andthe storage apparatus 100 using those flash memory modules P00-P33.However, the invention can be used not only in those flash memorymodules and storage apparatus, but also in flash memory modules havingother various configurations, storage apparatuses using those flashmemory modules as storage media, and address translation tableverification methods for the flash memory modules.

The invention can be widely used in various flash memory modules,storage apparatuses using those flash memory modules as storage media,and address translation table verification methods for the flash memorymodules.

1. A flash memory module comprising: a flash memory controller; and atleast one flash memory chip, the flash memory controller having memorythat stores an address translation table for translating between alogical page address and physical page address in the flash memory chip,and the flash memory controller controlling a first operation ofreading/writing data and a second operation of operating in an idlingstate at lower power consumption than in the first operation by haltingoperation, decreasing power supply voltage, or lowering operatingfrequency, wherein data in the address translation table is verifiedduring the second operation.
 2. The flash memory module according toclaim 1, wherein during the second operation, the flash memorycontroller alternately executes data verification in the addresstranslation table for a first time period and operation halt in theflash memory controller operation for a second time period, and whereinthe first period is shorter than the second period.
 3. The flash memorymodule according to claim 1, wherein error correction information isadded to the logical page address and the physical page address, andthey are store in the address translation table; whether or not anyerror has occurred is determined when verifying data in the addresstranslation table by verifying the logical page address, physical pageaddress, and error correction information stored in the addresstranslation table; if it is determined that an error has occurred in theaddress translation table and that error can be corrected with the errorcorrection information, a value corrected based on the error correctioninformation is stored in the address translation table; and if the errorcannot be corrected only with the error correction information, datarequired for data correction is read from the flash memory chip and theaddress translation table is reconfigured.
 4. The flash memory moduleaccording to claim 1, wherein the operation shifts from the firstoperation to the second operation according to an order from a hostdevice connected to the flash memory controller.
 5. The flash memorymodule according to claim 1, wherein the operation shift from the firstoperation to the second operation is controlled internally by the flashmemory controller.
 6. The flash memory module according to claim 1,wherein whether or not to perform data verification on the addresstranslation table during the second operation is set.
 7. The flashmemory module according to claim 1, wherein the operation shift from thefirst operation to the second operation and data verification in theaddress translation table are started after the completion of wearleveling processing performed by the flash memory controller.
 8. Theflash memory module according to claim 1, wherein the memory is SRAM. 9.A storage apparatus comprising: a flash memory module including a flashmemory chip and a flash memory controller for controlling dataread/write from/to the flash memory chip; and a storage controllerhaving cache memory that temporarily stores data read/written from/tothe flash memory chip, the flash memory controller having memory thatstores an address translation table for translating between a logicalpage address and a physical page address in the flash memory chip, andthe flash memory controller controlling a first operation ofreading/writing data and a second operation of operating in an idlingstate at lower power consumption than in the first operation by haltingoperation, decreasing power supply voltage, or lowering operatingfrequency, wherein the flash memory controller verifies data in theaddress translation table during the second operation.
 10. The storageapparatus according to claim 9, wherein the flash memory controllershifts from the first operation to the second operation after receivinga command from the storage controller.
 11. The storage apparatusaccording to claim 9, wherein the operation shift from the firstoperation to the second operation is controlled internally by the flashmemory controller.
 12. The storage apparatus according to claim 9,wherein a RAID group is comprised of combining a plurality of the flashmemory modules, and the storage controller issues a command so that ifone of the flash memory modules that belong to the RAID group shiftsfrom the first operation to the second operation, the other flash memorymodules also shift to the second operation.
 13. The storage apparatusaccording to claim 12 further comprising a spare flash memory modulethat verifies, after the address translation table is configured whenconnected to the storage controller, data in the address translationtable during the second operation, wherein if a failure has occurred inany of the flash memory modules, the data is rebuilt in the spare flashmemory module from the flash memory modules that belong to the same RAIDgroup as the defective flash memory module.
 14. The storage apparatusaccording to claim 13, wherein the flash memory module adds errorcorrection information to the logical page address and physical pageaddress and stores them in the address translation table; determineswhether or not any error has occurred by verifying the logical pageaddress, physical page address, and error correction information storedin the address translation table during data verification in the addresstranslation table; stores, if it is judged that an error has occurred inthe address translation table and that error can be corrected with theerror correction information, a value corrected based on the errorcorrection information in the address translation table; and reads, ifthe error cannot be corrected only with the error correctioninformation, data required for data correction from the flash memorychip and reconfigures the address translation table, and wherein whetheror not any failure has occurred in the flash memory module is determinedbased on whether or not the number of errors found during the dataverification that cannot be corrected only with the error correctioninformation is a prescribed number or larger.
 15. The storage apparatusaccording to claim 9, wherein the flash memory module is connected tothe storage controller via a first network for transmitting/receivingdata read/written from/to the flash memory chip, and a second networkfor transmitting/receiving data for controlling electric power consumedduring the second operation.
 16. A data verification method for astorage apparatus including: a flash memory module including a flashmemory chip and a flash memory controller having memory that stores anaddress translation table for translating between a logical page addressand a physical page address in the flash memory chip, the flash memorycontroller controlling data read/write from/to the flash memory chip andalso controlling a first operation of data read/write and a secondoperation of operating in an idling state at lower power consumptionthan in the first operation by halting operation, decreasing powersupply voltage, or lowering operating frequency; and memory fortemporarily storing data read/written from/from the flash memory chip,the method comprising verifying data in the address translation tableduring the second operation.
 17. The data verification method for astorage apparatus according to claim 16, further comprising shifting theoperation from the first operation to the second operation afterreceiving a command from the storage controller.
 18. The dataverification method for a storage apparatus according to claim 16,further comprising shifting the operation from the first operation tothe second operation, the shift being internally controlled by the flashmemory controller.
 19. The data verification method for a storageapparatus according to claim 16, further comprising shifting, if one offlash memory modules combined to configure a RAID group shifts from thefirst operation to the second operation, the operation in the rest ofthe flash memory modules that belong to the RAID group to the secondoperation.
 20. The data verification method according to claim 19,further comprising rebuilding, if a failure occurs in any of the flashmemory modules, data in a spare flash memory module that verifies datain the address translation table during the second operation from theflash memory modules that belong to the same RAID group as the defectiveflash memory module instead of from the defective flash memory module.